Exemplary embodiments relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a three-dimensional (3-D) non-volatile memory device and a method of manufacturing the same.
A non-volatile memory device retains data although power is off. A 3-D non-volatile memory device may have a higher data capacity and a higher integration degree than a 2-D non-volatile memory device.
The structure of a conventional 3-D non-volatile memory device and features thereof are described below.
FIG. 1A is a cross-sectional view showing the structure of an exemplary 3-D non-volatile memory device according to the conventional technology.
As shown in FIG. 1A, the 3-D non-volatile memory device according to the conventional technology includes a plurality of memory cells MC stacked along channels CH protruding from a substrate 10. The plurality of memory cells MC is coupled in series between a lower select transistor LST and an upper select transistor UST to form one string. Furthermore, a bit line BL is coupled to the channels CH.
In FIG. 1A, reference numerals ‘11’ and ‘16’ denote a gate insulation layer, reference numeral ‘13’ denotes a lower select line, reference numeral ‘15’ denotes a word line, and reference numeral ‘17’ denotes an upper select line. Furthermore, reference numeral ‘12’ denotes an interlayer dielectric layer, which is formed of an oxide layer.
The structure of FIG. 1A has an RC delay because the word lines 15 are extended in a specific direction. In order to prevent the RC delay, a resistance of the word lines 15 may be reduced by siliciding the edge regions of the word lines 15.
If the number of stacked memory cells MC is increased in order to increase the degree of integration in the memory device, the total thickness of the memory stack is increased. By increasing the thickness of the memory device, an etch process may be more difficult. Furthermore, a capacitance between conductive lines varies, and a gap-fill margin is reduced, and thus gap-filling characteristics vary for the conductive lines. Furthermore, the electrical properties of the memory device are deteriorated because of disturbances generated between the word lines. A method of reducing the thickness of the interlayer dielectric layer 12 that reduces the total thickness of a memory stack may address some of the above described features of the memory devices.
FIG. 1B is an enlarged cross-sectional view of the word line regions of the 3-D non-volatile memory device according to the conventional technology. FIG. 1B is an enlarged cross-sectional view of a region A in FIG. 1A.
If the edge regions 15A of the word lines 15 are silicided as shown in FIG. 1B, RC delay may be reduced to some extent because the resistance of the edge regions 15A is lowered. If the edge regions 15A are silicided, current mostly flows through the edge regions 15A of the word lines. However, RC delay may still remain because the capacitance between the neighboring word lines 15 or 15A (as denoted by the capacitor symbol illustrated in FIG. 1B) is great because the interlayer dielectric layer 12 exists between the neighboring word lines 15 and 15A.
More specifically, if the thickness of the interlayer dielectric layer 12 is reduced so as to reduce the total thickness of the memory stack, RC delay increases because the capacitance between the neighboring word lines 15 or 15A is further increased.